Comparison of NULL Convention Booth2 Multipliers
نویسندگان
چکیده
This paper describes two architectures for designing asynchronous NULL Convention Logic (NCL) Booth2 multipliers. The first is better suited for a non-pipelined implementation, while the second is best for a high throughput pipelined realization. The two architectures are compared in terms of area and speed, using a gate-level NCL VHDL library with gate delays generated from physical level simulation of a 1.8V, 0.18um TSMC CMOS process. Keywords-computer arithmetic; asynchronous; clockless; delayinsensitive; NCL
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تاریخ انتشار 2010